1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a decoupling capacitor, and, more particularly, to a semiconductor integrated circuit device with an improved device integration density.
2. Description of the Related Art
As operational frequencies of semiconductor integrated circuit devices have become increasingly higher, there is a tendency for the wiring area allocated to the power supply wire and ground wire to also become larger. Thus, when a semiconductor integrated circuit device operates at high frequency, a variation in power supply voltage, such as temporary current spike, is likely to occur.
As a conventional scheme to suppress this variation in power supply voltage, there is known a technique of connecting a decoupling capacitor in parallel to the power supply. This connection can reduce power supply noise and suppress a variation in power supply voltage, which leads to 1) prevention of the malfunction of a semiconductor integrated circuit originated from power supply noise and, 2) a variation in power supply voltage. To achieve the above object, the size of the decoupling capacitor connected to the power supply should be set to several tens of nF with respect to a single chip or package. In the conventional semiconductor integrated circuit device, an exclusive layout area for a decoupling capacitor is provided at each side of space between the core portion or the device forming region and the I/O portion, and the decoupling capacitor is formed by MOS (Metal Oxide Semiconductor).
However, in a conventional semiconductor integrated circuit device the need for the exclusive layout area for a decoupling capacitor increases the device area and lowers the device integration density.
An example of a solution to this problem, Japanese Patent Laid-Open No. 12825/1998, discloses a technique of forming a polycrystalline silicon layer on the device side of a semiconductor substrate and forming a decoupling capacitor between the polycrystalline silicon layer and the top surface of the semiconductor substrate. The technique this patent describes eliminates the need for the exclusive layout area for a decoupling capacitor.
Due to the decoupling capacitor formation on the device side of a device forming region according to the conventional technique, a problem arises in that the area of the device forming region increases.
Japanese Patent Laid-Open No. 2002-124636 discloses a technique of providing a multilayer wiring structure on a semiconductor element and forming 1) an electrode, 2) a dielectric film and 3) an electrode on the multilayer wiring structure in the named order; thereby forming a decoupling capacitor. Japanese Patent Laid-Open No. 2002-124636 describes that this technique allows a large-capacitance decoupling capacitor to be provided in a semiconductor device.
However, the above conventional technique has a problem. Because a decoupling capacitor is provided on the multilayer wiring structure according to the technique described in Japanese Patent Laid-Open No. 2002-124636, pad electrodes cannot be provided in the region on the multilayer wiring structure where the decoupling capacitor is provided. This restricts the layout of the semiconductor integrated circuit device and enlarges it as a consequence. Also, providing a decoupling capacitor on the multilayer wiring structure requires at least the step of forming a lower electrode layer, the step of forming a dielectric layer and the step of forming an upper electrode layer, which complicates the fabrication process for the semiconductor integrated circuit device and increases the fabrication cost.